A review of PCB-level power delivery system

Focus:

This paper is a short primer on the design and analysis of power delivery systems (PDSs), also known as power distribution networks (PDNs), which are formed by the on-chip, IC package-level, and board-level interconnects used to distribute power to chips in high-speed systems. The paper begins by reviewing power delivery challenges, the elements of a PDS, and the objectives in designing a PDS. The importance of dc IR drop, factors affecting IR drop, and the role of IR drop analysis are explained. The importance of impedance and the role of impedance analysis in PDS design are explained and design practices used to reduce PDS impedance are discussed. Simulations illustrate the influence of a VRM and decoupling capacitors on PDS impedance, illustrating how decoupling caps are used to “tune” this impedance and minimize power ground noise. Article concludes by discussing the limitations of board-level decoupling capacitors at higher frequencies and the need to apply decoupling at the IC package and die levels, which will ultimately lead to a system-level approach to PDS design.

What you’ll learn:

• How to understand the role and behavior of power distribution systems in the design of high-speed digital systems
• How to understand the role of IR drop and impedance analysis in designing power distribution systems
• How to understand the role of decoupling capacitors in the design of high-speed digital systems and chips

View the Source

Author & Publication:

Jin Zhao, Sr. Technical Staff Member, and Raymond Chen, Vice President, Sigrity Inc., Vendor website, May 20 2006

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