Frequency-Foldback Technique Optimizes PFC Efficiency Over The Full Load Range

Focus:

So-called green requirements such as 80 PLUS aim to maximize power supply efficiency across a range of load conditions. So it has become critical that power supply designers address medium- and light-load efficiency in the PFC power stage. A popular approach is to reduce the switching frequency (frequency foldback.) While extremely efficient at very low power, this solution must be carefully implemented at intermediate power levels. This article clarifies how the switching frequency should be managed in a PFC boost converter to maximize efficiency across the load range. Instead of computing the switching losses of a PFC boost converter directly, this article describes an easier approach—predicting the trend in discontinuous conduction mode (DCM) losses as a function of critical conduction mode (CrM) losses, with respect to switching frequency reduction. The analysis shows that frequency foldback is preferred when conduction losses are small compared to switching losses, that is, when the line current is low. This is the basis for current-controlled frequency foldback (CCFF), which is explained here, and which has been implemented in some ON Semiconductor controllers. Their operation and experimental results are discussed here. Comparisons are made between CCFF with and without cycle skipping [pulse skipping], and between CCFF and CrM operation. Frequency-clamped CrM is also discussed and an appendix gives background on this and other existing methods for improving PFC efficiency at light loads.

What you’ll learn:

• How to understand the operation and benefits of current-controlled frequency foldback in PFC boost converters
• How to improve the efficiency of PFC power stages across the full load range

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Author & Publication:

Joel Turchi, ON Semiconductor, Toulouse, France, How2Power Today, Oct 25 2012

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