SEPIC-Fed Buck Topology Boosts Performance in Non-Isolated DC-DC Converters

Focus:

This article begins by outlining the limitations of synchronous buck converters in powering FPGAs and ASICs. These converters are required to supply high current at low voltage, but at the same time, it’s desired that they provide high efficiency over load, fast transient response, low cost and other characteristics. However, the limitations of the buck topology mean that tradeoffs must be made. After discussing these limitations, this article introduces a new topology that overcomes them--the SEPIC-fed buck. A simple schematic is given for this topology, the key power switch and inductive components are identified and results are shown for the converter’s efficiency and transient response. The reduction in output capacitance versus other solutions is described and there is a vague description of how the converter reduces losses. What’s missing is a detailed description of how the converter operates.

What you’ll learn:

• How to achieve higher efficiency and faster transient response in point-of-load regulators

Notes:

This article appears on pages 42-44 of the March 2014 issue of Bodo's Power Systems. CUI has also posted a version of the article at http://www.cui.com/catalog/resource/sepic-fed-buck-topology-boosts-performance.pdf .

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Author & Publication:

Dr. Fariborz Musavi, Director of Engineering, CUI, Bodo's Power Systems, Mar 01 2014

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