The Engineer’s Guide To EMI In DC-DC Converters (Part 6): Mitigation Techniques Using Discrete FET Designs Focus: This part 6 explores EMI abatement in dc-dc regulator circuits that employ a
controller driving a discrete pair of high- and low-side power MOSFETs. This article
provides guidelines for laying out a multilayer PCB of a half-bridge design with
MOSFETs and controller to achieve excellent EMI performance. The imperative is to
minimize critical loop parasitic inductances by careful power-stage component
selection and PCB layout. A layout example demonstrates that it’s possible to reduce
the generation of conducted EMI without sacrificing efficiency or thermal performance.
Article begins by briefly describing the sources of EMI in these converters, followed
by a very detailed list of guidelines for PCB layout design for low EMI. Next is a
short case study of a synchronous buck converter based on the LM5146 controller
including two lateral-loop layout designs. The last section presents an improved
layout that reduces EMI. Concepts described here for the buck can be extended to any
dc-dc regulator topology.
What you’ll learn: - How to reduce EMI generation in dc-dc converters based on a controller with external
MOSFETs
- How to optimize PCB layout of dc-dc converters for EMC
View the Source
Author & Publication: Timothy Hegarty, Texas Instruments, Phoenix, Ariz, How2Power Today, Sep 14 2018
|
This article summary appears
in the HOW2POWER Design Guide.
The Design Guide offers
organized access to
hundreds of articles
on dozens of power conversion
and power management topics.
The Design Guide search results
include exclusive summaries
and accurate "how to" analysis
to help you make faster,
more informed decisions.
Search
for more
articles
|